The present invention relates to the field of Flash Memory Systems. More particularly, the present invention relates to Flash Memory Systems interfacing with Host Systems.
Flash memory technology is an electrically rewritable nonvolatile digital memory medium. Being non-volatile, it does not require a sustained voltage to retain digital data within its memory. A flash memory cell typically stores charge on a floating gate to represent a first logic state in the binary state system, while the lack of stored charge represents a second logic state in the binary state system. Flash memory cells typically support a write operation, a read operation, and an erase operation.
As flash memory technology has advanced, a variety of applications has become possible. In particular, flash memory implementations that emulate the mass storage function of conventional rotating magnetic media, e.g., a hard disk drive or a floppy disk drive, coupled to a host computer system or other host digital system have gained wide acceptance. Hard disk drives and floppy disk drives suffer several deficiencies which are not shared by flash memory technology. First, hard disk drives and floppy disk drives have many moving parts, e.g. an electrical motor, a spindle shaft, a read/write head, and a magnetizable rotating disk. These components give rise to reliability problems and magnify the hard disk drive""s and floppy disk drive""s susceptibility to failure resulting from the vibration and shock of being dropped or bumped. Secondly, a motor driven disk drive consumes a significant amount of power, substantially shortening the operational time between battery chargings. Finally, accessing data stored in the hard disk drive or the floppy disk is a relatively slow process.
In contrast, a Flash Memory System possesses many advantages over rotating storage disks. The typical Flash Memory System has no moving parts, accounting for the higher reliability of the typical Flash Memory System. In addition, the rugged design of the typical Flash Memory System withstands environmental conditions and physical mishandling that would otherwise be catastrophic to the hard disk drive or the floppy disk drive. Generally, a user can access data stored in the typical Flash Memory System fairly quickly. Finally, the power consumption of the typical Flash Memory System is considerably lower than the hard disk drive""s and the floppy disk drive""s power consumption.
Because of the market saturation and universal application of rotating media such as hard disk drives, even a superior process or device seeking to capture a share of the market must be compatible with existing software and operating systems. To achieve compatibility with systems configured to store data within legacy rotating mass storage systems, flash memory is typically broken up into a series of data fields capable of storing five hundred twelve bytes of user data and sixteen bytes of overhead data, thereby emulating the size of a data field typically available in commercial hard disks. FIG. 1 depicts a non-volatile memory array within a flash memory device. A collection of Physical Sectors or Pages 108, . . . 112 are typically capable of storing of five hundred twelve bytes of user data plus sixteen bytes of overhead data per Page, thereby conforming to the storage capacity of a sector of a typical rotating storage device. A plurality of Physical Pages 108, . . . , 112, typically sixteen or thirty two Pages, comprise a Physical Data Block 102.
According to the prior art, a Flash Memory System has been comprised of a single memory structure 100 comprising a plurality of Physical Data Blocks 102, . . . 106. Each data Physical Data Block 102, . . . , 106 is uniquely assigned a Virtual Physical Block Address (VPBA), for identifying and distinguishing a plurality of Physical Data Blocks comprising a Flash Memory System. Usually, each data block 102, . . . , 106 is selectively programmable and erasable.
FIG. 2 illustrates one embodiment of flash memory architecture according to the prior art. A Host 215, such as a computer or digital camera, transmits and receives data to a removable flash memory card 201. During transmission from the Host to the Flash Memory System, the Host assigns logical block addresses to the data. When retrieving the data, the Host requests data according to the logical block addresses which it previously assigned. The data enters a host interface circuit 203 of the flash memory Controller 202, by means of a host interface bus 220, typically comprising parallel bus architecture. The host interface circuit controls the storage of incoming data by means of a RAM Data Buffer 204. When a predetermined amount of data has been stored within the RAM Data Buffer 204, the memory interface circuit 205 transmits data through a memory bus 230 to the non-volatile Flash Memory Unit 206, which was disclosed in greater detail according to FIG. 1. Typically the data bus 230 is a parallel bus structure. The size of the data buffer 204 is advantageously designed to store an amount of data equal to a multiple of some non volatile memory field, such as a page comprising approximately five hundred twenty eight total bytes of data, depicted in FIG. 1.
At the present state of technology, a Flash Memory System has a limited number of program cycles before xe2x80x9cwearing out.xe2x80x9d To ameliorate the problem of wearing-out, a controller discussed in greater detail in FIG. 2 attempts to cycle through the available memory locations before returning to the first location. By regulating the rate of wear among cells, the controller prevents uneven wear focusing on one area of the Flash Memory System. As a consequence of wear-leveling programs, all the cells within a Flash Memory System will therefore typically wear-out at the same rate. The wear-leveling program therefore reduces the likelihood that the Flash Memory System will experience premature degradation within a localized memory area due to overuse of one area. The entire Flash Memory System therefore remains uniformly reliable through its life. A hard disk drive does not require this wear leveling feature because its storage mechanisms can undergo a practically unlimited number of program/write operations without degrading performance. This contrast results in an operational disparity between the addressing system used within a flash memory, and that used within a hard drive or floppy disk.
In both hard drives and Flash Memory Systems, the physical addresses assigned within a memory typically follow a geometric structure within the memory system. That is, physical addresses will typically increment through successive memory locations. When User Data is received by a memory system, whether Flash Memory or rotating disk, a Host system normally assigns an address to incoming data. In a hard drive, data is typically stored in the sector whose physical address matches the logical address defined by the Host System. If a Host system updates User Data previously defined by a specific logical address, the new data will overwrite the original data at the prescribed address.
In a Flash Memory System, however, as a result of cycling through various areas of a flash memory according to a wear-leveling algorithm, physical areas defined by new physical addresses are continually filled. When a Host system updates User Data defined by a specific logical address and sends it to the Flash Memory System, the wear-leveling program will assign the incoming User Data to a physical location unrelated to the physical location in which User Data of the same logical address had previously been stored. Old data associated with a particular logical address is not immediately overwritten by incoming data of the same logical address. The old data is simply obsoleted, and the incoming data is written into the next available Physical Data Block, that is, the next addressable Physical Data Block that is free and non-defective. As a result, the Host assigns addresses to data that bear no relationship to the addresses where the flash memory ultimately stores the data. A distinctive characteristic of the wear-leveling data storage program implemented by the typical Flash Memory System therefore lies in the continuously changing relation between the logical addresses assigned by the Host, and the physical addresses actually used by the Flash Memory System. Through this dual memory process, a Flash Memory System is able to functionally emulate the relationship between a hard drive and a Host with respect to data storage and retrieval, thereby maintaining compatibility with existing software.
FIG. 3 illustrates various registers and fields used to take incoming data and store it within the Flash Memory Unit 206 (FIG. 2). In order to facilitate retrieval of User Data stored by a Host System, however, a correlation of logical and physical addresses must exist. This correlation is typically stored within the Flash Memory System, in the overhead portions of each page 108, . . . 112, and in the RAM Space Manager 370. When a Host transmits User Data 310, . . . , 316 identified by a set of logical addresses 302, . . . , 308 to a Flash Memory System, the Flash Memory System stores the data in certain physical locations 322, . . . 328 and then correlates the logical 302, . . . , 308 and physical 330, . . . , 336 addresses of that data in specifically designated correlation registers or fields such as the space manager 370. Subsequently, when the Host requests data identified by a specific logical address, the Flash Memory System examines the various registers, fields, or files correlating logical addresses to physical addresses. Upon locating the logical address requested by the Host, the Flash Memory System is able to secure the Physical Address correlating to that logical address. The Flash Memory System retrieves the User Data from that physical address.
The storage and retrieval process involves a series of operations of masking and concatenating various bits within various address registers. The bit register used to store a Logical Block Address can be divided into two sub-registers, a higher order bit field 342 and a lower order bit field 344 of LBA temporary register 340. A group of Logical Blocks 310, . . . , 316, typically sixteen or thirty two, defined by a common address within the higher-order bit field comprise a Virtual Logical Block 300. The number in the higher-order bit field is the Virtual Logical Block Address. The number in the lower order bit fields among the component Logical Blocks is an LBA offset which distinguish the individual Logical Blocks. The lower order addresses or offsets typically increment from zero through fifteen or zero through thirty-one, though any size Virtual Logical Block is possible. The higher order Virtual Logical Block address plus the lower order bits define a Logical Block address, as illustrated by LBA temporary register 340. Component Logical Blocks 310, . . . , 316 within a Virtual Logical Block are therefore defined by a Logical Block Address (LBA).
A Virtual Logical Block (VLB) 300 of data, defined by a Virtual Logical Block Address (VLBA) represents an amount of data equivalent to a physical area of memory known as a Physical Data Block 320 which is defined by a Virtual Physical Block Address (VPBA). A VPBA is comprised of complement Physical Pages. Consecutive pages within a VPBA are distinguished by PBA offset. The VPBA plus the PBA offset define a unique PBA or Physical Block Address 330, . . . , 336 for each page. Each Logical Block 310, . . . , 316 represents an amount of data equivalent to a physical Page 322, . . . , 328. Data fields and registers dedicated to correlating logical and physical addresses, such as a RAM Space Manager 370 consume valuable memory space within a Flash Memory System, memory that could otherwise be advantageously used to store User Data. If a Flash Memory System were comprised of sufficient correlation registers 380, . . . , 384 to correlate every LBA 345, 346, etc. to a respective PBA 330, . . . , 336 a great deal of Flash Memory would be consumed in the correlation function, leaving far less available memory for storing User Data. Such detailed correlation would be required, for example, if a Virtual Logical Block of User Data 300 were fragmented into sixteen or thirty-two component LBA""s 302, . . . , 308 and stored in sixteen or thirty-two diverse pages distributed among different Physical Data Blocks within the Flash Memory System 200.
One way of minimizing that consumption of memory space devoted to correlation data is to limit correlation to larger groups of data, such as correlating Virtual Logical Blocks Addresses to Virtual Physical Block Addresses defining large blocks of physical memory. One way of retaining a correlation between component Logical Blocks of a VLB and individual Physical Pages of a Physical Data Block without multiplying correlation registers to include every Logical Block is to store consecutively addressed Logical Blocks 310, . . . , 316 of VLB 300 in consecutively addressed pages 322, . . . , 328 within a Physical Data Block 320. A one-to-one correlation between consecutive Physical Block Addresses 330, . . . , 336 within a Physical Data Block 320 and component Logical Block Addresses 302, . . . , 308 within a Virtual Logical Block 300 are thus retained through a spacial or quasi-spacial arrangement. No register need be devoted to correlating individual LBA""s with individual Physical Page addresses. Only the VLBA in the high order bit field need be correlated to the VPBA representing the Physical Data Block.
FIG. 4 is a flow chart illustrating the storage of incoming User Data according to the data fields and registers of FIG. 3. In the first step 402, Virtual Logical Block seventeen 300 (FIG. 3) is received from a Host 215 for storage in a non-volatile Flash Memory Unit 206 (FIG. 2). In the following step 404, the Controller 202 moves the first LBA 302 to the temporary LBA Register 340. Next 406, the Controller masks the lower order bits 344 within the temporary LBA Register 340, and moves the VLBA 342 into a VLBA Register 360. In the next step 408, the Controller examines the Space Manager 370 and identifies VPBA correlation register 384 corresponding to the current VLB 349 as disclosed in the VLBA register 360. In the next step 412, the Controller 202 identifies a free and non-defective Physical Data Block 320 identified by a new VPBA. In the following step 414, the Controller 202 writes the new VPBA in the correlation register 384 of the Space Manager 370.
The Controller is now ready to identify specific pages 322, . . . , 328 within the select Physical Data Block 320 for storing incoming User Data within the incoming Virtual Logical Block 300. To achieve a one-to-one correlation between consecutive Logical Blocks 310, . . . , 316 within the Virtual Logical Block 300, and consecutive Physical Block Addresses 330, . . . , 336, the Controller combines the VPBA of the Physical Data Block 320 with the LBA offset of the current LBA 302, . . . , 308. In step 415 the Controller 202 stores the VPBA of the select Physical Data Block 320 in a temporary PBA register 351. In step 416, the Controller 202 masks the higher order bits 342 of the temporary LBA register 340 and concatenates the lower order bits 344 containing the LBA offset into the lower order register 354 of the temporary PBA register. The combined upper 352 and lower 354 registers from the temporary PBA register 351 form a Physical Block Address. In step 418, the processor then programs the Logical Block of data 310, . . . 316 identified by the temporary LBA Register 340 into the physical page 322, . . . , 326 identified in the temporary PBA Register 351.
In step 420, the controller examines the next Logical Block of incoming data, and moves the LBA of the incoming Logical Block into the temporary LBA register. According to the final step 422, if the value in the VLBA Register 360 remains unchanged, the Controller 202 returns to step 416. If the new User Data received from the Host 215 comprised a new VLBA, the process returns to step 402 and resumes.
Some of the steps in FIG. 4 could be performed in a different order without changing the outcome of the process. Because the specific mechanics of storage could be performed in a number of equivalent ways, the process disclosed in FIG. 4 is not intended to suggest that a correlated storage process according to the prior art necessarily follows these exact steps. The details are disclosed simply to illustrate one way of performing a data storage process in a manner that preserves a natural correlation between LBA""s and PBA""s. According to the process as described above, the LBA offset 344 is used as a PBA offset 354 when storing a VLB into a Physical Page. Because of the order preserved in the storage or programming process, individual LBA""s requested by the Host 202 may be retrieved by the Flash Memory System 201.
FIG. 5 discloses a process according to the prior art whereby data is retrieved from the Flash Memory Unit 206 upon request from the Host 202. Again, the retrieval steps listed below are exemplary of data retrieval according to the prior art, and is not intended to limit the retrieval of data to any single algorithm according to the prior art. According to step 502, the Host 202 (FIG. 2) requests retrieval of data defined according to a particular LBA or group of LBA""s 302, . . . , 308 (FIG. 3). In step 504, the Controller 202 moves the requested LBA 302, . . . , 308 to a temporary LBA register 340, conceptually depicted as comprising an upper 342 and lower 344 register of higher order bits and lower order bits respectively. In the next step 506, the Controller 202 masks out the lower order bits 344 and defines the requested VLBA in a temporary VLBA register 360 according to the value within the higher order register 342. In the following step 508, the Controller 202 increments the Space Manager 370 to the VLBA in the temporary VLBA register 360, thereby accessing the current correlation register 384 corresponding to the VLBA found in the temporary VLBA register 360. In step 510, the Controller 202 copies the VPBA found in the current correlation register 384 into the upper register 352 of the temporary PBA register 351. In the following step 512, the Controller 202 masks the higher order bits within the upper register 342 of the temporary LBA register 340 and concatenates the lower order bits within the lower register 344 containing the LBA offset into the lower order register 354 of the temporary PBA register 351. The combined upper 352 and lower 354 registers of the temporary PBA register 351 form a Physical Block Address. The Controller 202 is now able, according to step 514, to access the Physical Data Block defined by the Physical Block Address constructed within the temporary PBA register, and forward the User Data found therein to the Host. According to step 516, the controller also forwards the Logical Block Addresses in the temporary LBA Register to the Host, thereby defining the Logical Block of User Data according to the original address ascribed to it by the Host.
By concatenating the LBA offset onto a VPBA during the storage and retrieval process, the Controller is able to create an LBA to PBA correlation upon request, and need only store a correlation between the VLBA and the VPBA in the Flash Memory System 201, reducing the amount of memory necessary for correlation to only a fraction of what would be necessary without this process. Accordingly, when the Host requests the data defined by a series of Logical Block Addresses, the Flash memory retrieves the User Data from a physical location, and returns it to the Host. When the Host retrieves data therefore, the data sent to the Host is identified by the same address which the Host requested. The dual addressing scheme and cross referencing used within the Flash Memory System is invisible to the Host.
Although flash memory is typically much faster than rotating disk type memory, there is a wide disparity between the xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d times within flash memory. The read time of flash memory is on the order of microseconds, and compares favorably with RAM type memory. The programming or write operation to Flash Memory, however, is on the order of milliseconds, typically slower by powers of ten than the programming time typically found in RAM type memories. Accordingly, the RAM Data Buffer 204 is able to receive and retransmit digital data far faster than the non-volatile memory unit 206 is able to receive it. The programming phase of a Flash Memory System therefore becomes a major factor limiting the potential speeds possible through integrated circuit and MOS system incorporating Flash Memory components.
The speed of programming Flash Memory was substantially improved by the development of a multi bank Flash Memory System as seen in FIG. 6. A Flash Memory System 600 is operatively connected to a Host system 601 such as a computer or digital camera. A controller 604 comprising a Host Interface Circuit 605, a Data Buffer 607 and a Memory Interface Circuit 609 is operatively coupled to a Flash Memory Unit 602. The Flash Memory Unit 602 is comprised of a plurality of Memory Banks 621, . . . , 627. The first Bank 621 is comprised of a plurality of Physical Data Blocks 631, . . . , 637 and a single RAM Data Register 613. The second Bank 623 is comprised of a plurality of Physical Data Blocks 641, . . . , 647 and a single RAM Data Register 615. The third Bank 625 is comprised of a plurality of Physical Data Blocks 651, . . . , 657 and a single RAM Data Register 617. The fourth Bank 627 is comprised of a plurality of Physical Data Blocks 661, . . . , 667 and a single RAM Data Register 619. Typically, each of the plurality of Memory Banks 621, . . . , 627 are comprised of an equal number of Physical Data Blocks. Typically, each RAM Data Register 613, . . . , 619 has a data capacity equal to one Page of physical memory, which is typically capable of holding five hundred twelve bytes of User Data plus sixteen bytes of overhead data. The Flash Memory Unit 602 of FIG. 6 is comprised of four Memory Banks 621, . . . , 627 for exemplary purposes only. Multi-bank flash memories could be comprised of any number of memory-banks. Similarly, the size of data fields and memory areas are for exemplary purposes, depicting the more common configurations found according to the prior art. Neither these depictions of the prior art, nor its application to the present invention is intended to restrict the application of the present invention to any specific number of Memory Banks. Neither are the illustrations contained herein intended to restrict the sizes of data fields and registers, whether physical or logical, nor restrict an amount of incoming data being stored or processes. Rather, specific parameters such as sizes of data fields, the number of sub-groupings of physical memory comprising a larger memory component, or the number of sub-groupings comprising a larger group of data, are offered for illustrative purposes only, and have been selected to represent quantities frequently found in the prior art.
In multi-bank Flash Memory Systems 600, the RAM Data Buffer 607 does not directly store data into Flash Memory Blocks 631, . . . , 667. Rather, the RAM Data Buffer 607 loads data in to the plurality of RAM Data Registers 613, . . . 619, which then simultaneously load User Data into their respective Memory Banks 621, . . . 627. Each RAM Data Register 613, 615, 617, 619 is typically capable of storing and programming one page of data.
As the Flash Controller 604 receives information from the Host 601, the Host Interface Circuit 605 queues the information in the RAM Data Buffer 607. When the RAM Data Buffer 607 is filled according to a predetermined amount of data, the memory interface circuit 609 begins writing data from within the RAM Data Buffer 607 to select RAM Data Registers from among the plurality of RAM Data Registers 613, 615, 617, 619 within the Flash Memory Unit. In the four-bank Flash Memory Unit 602 depicted in FIG. 6, the Buffer 607 would typically store four pages of data. According to the most advantageous designed, the number of select RAM Data Registers typically equals the number of Virtual Logical Blocks of incoming data. Data Bus 611 is a parallel bus structure for moving data from the Data Buffer 607 to the Data Registers 613, 615, 617, 619. Because the RAM Data Buffer 607 and the RAM Data Registers 613, 614, 617, 619 are random access memory structures, the read and write times between these structures is extremely fast. After the select RAM Data Registers 613, . . . , 619 have filled, the individual RAM Data Registers 613, . . . , 619 simultaneously begin writing data to flash memory areas within their respective Memory Banks 621, . . . , 627. In a four bank system, programming time is reduced to approximately xc2xc the time required in a traditional Flash Memory Unit. In a ten bank system, programming time with the reduced to approximately one tenth the programming time required by a traditional flash Memory Unit. A multibank system is therefore faster than a traditional Flash Memory Unit by a factor equal to the number of Ram Data Registers simultaneously engaged in programming User Data into a Flash Memory Unit.
Although the transmission and programming time from the RAM Data Buffer 607 to the RAM Data Registers 613, . . . , 619 is negligible when compared against the programming time for the Flash Memory cells, advanced designs can substantially reduce the time expended on writing User Data from the RAM Data Buffer 607 to RAM Data Registers 613, . . . , 619. FIG. 7 discloses a Memory Unit comprised of multiple Memory Banks 702, 704, 706, 708. A distinctive feature of this embodiment, however, is the presence of dual RAM Data Registers 710 and 720, 712 and 722, 714 and 724, 716 and 726, respectively assigned to each individual Memory Bank 702, . . . , 708. Each Memory Bank 702, . . . , 708 individually comprises a primary Register 710, 712, 714, 716 and an auxiliary Register 720, 722, 724, 726. According to this embodiment, the RAM Data Buffer 730 loads the four respective primary Registers 710, . . . , 716 with data to be stored in the Flash Memory cells of the respective Memory Banks 702, 704, 706, 708. Again, for continuity of the comparison, it is be assumed that there are a total of four Virtual Logical Blocks of incoming User Data, each VLB comprising thirty-two Logical Blocks of User Data, are to be distributed among the four Memory Banks 702, 704, 706, 708. Each Memory Bank 702, 704, 706, 708 will therefore receive one Virtual Logical Block, or thirty-two Logical Blocks data, programmed one page at a time, plus the overhead data associated with each page. This process will occur over thirty-two cycles.
By advantageously alternating between the primary Registers 710, . . . 716 and auxiliary Registers 720, 722, 724, 726, a time delay in writing data from the RAM Data Buffer 730 to the RAM Data Registers 710, . . . 726 would occur only on the first cycle of writing of the first four pages of data to the four respective registers. Programming of the Flash Memory of the respective Banks 702, . . . , 708 takes far longer than loading a page of memory into a RAM Data Registers. Therefore, as the primary Registers 710, . . . , 716 are programming their respective pages of data into the Flash Memory Cells of their respective Memory Banks 702, . . . , 708, the RAM Data Buffer 730 can load a next four pages of data into the four auxiliary Registers 720, . . . , 726. Because this takes place while the Flash Memory cells are being programmed by their respective primary Registers 710, . . . 716, there is no actual delay imposed in the writing of the auxiliary Registers 720, . . . , 726. When the primary Registers 710, . . . , 716 have finished loading their respective pages of data into the Memory cells of their respective Memory Banks 702, . . . , 708, the auxiliary Registers 720, . . . 726 are immediately ready to begin loading their respective pages of data into their respective Memory Banks 702, . . . 708. During the programming of the auxiliary registers 720, 722, 724, 726 into their respective Physical Data Blocks, the RAM Data Buffer 730 can simultaneously load the next cycle of data into the primary registers. This process of simultaneously loading data into one set of registers while a complimentary set of registers programs select Flash Memory cells continues until the select data has been loaded into the Flash Memory. As noted, the only delay imposed by the loading of data from the RAM Data Buffer 730 into the respective RAM Data Registers 710, . . . , 716 occurs during the first cycle.
Assuming that each RAM Data Register has a capacity of one page of data, which is roughly equal to one Logical Block of User Data; where N=the total number of Memory Banks being utilized in a programming operation according to the present invention, p=the total number of pages to be loaded, t=the amount of time to load a single page of data into a single RAM Data Register or RAM Data Buffer, and T=the amount of time required to program a single page of data into Flash Memory, the following table compares the programming speeds according to the prior art FIG. 2, multiple Memory Banks with a single RAM Data Register per Memory Bank according to the present invention (FIG. 6), and multiple Memory Banks with dual RAM Data Registers according to the present invention (FIG. 7):
The programming times for the above table assumes that the Data Bus 611, 740 of the multi bank systems carries data at the same rate as the Data Bus 230 of a traditional Flash Memory Unit. If Data Bus 611, 740 according to the current invention could program all RAM Data Registers 710, . . . , 716 simultaneously through a parallel configuration, the above equations would have to be altered slightly.
Returning to the discussion according to FIG. 6, according to the above illustration, N Memory Banks per Memory Unit effectively results in a total programming time that is N times as fast as an application with a traditional Flash Memory Unit. On first blush, this would appear to invite the construction of Memory Units comprising hundreds of Memory Banks. Although there is no theoretical limit to the number of Memory Banks that might be incorporated within a multi-bank Flash Memory Unit, operational parameters according to a particular application will typically dictate practical limits to the number of Memory Banks that can be effectively utilized.
According to the prior art, multi-bank Flash Memory units were programmed according to an interleaving process, illustrated in conjunction with FIG. 8. According to the following illustration, it is assumed for exemplary purposes only that each VLB comprises thirty-two individual Logical Blocks in four Physical Data Blocks. It is also assumed for exemplary purposes that each Register 840, . . . 846 programs one Page of User Data per cycle, one Page corresponding to one Logical Block of User Data. Four consecutive VLB""s of User Data contain one-hundred twenty eight Logical Blocks 810, . . . , 826 of data, which may be represented either by an address, or an offset number measured against the total number of Logical Blocks in the incoming set of User Data 802. For example, the third Logical Block 825 within the fourth Virtual Logical Block 806 can be represented either by the address 24:2, indicating VLBA 24, offset 2, or simply according to the total offset number 98, measured against all one hundred twenty-eight Logical Blocks in the incoming set of User Data 800. Four consecutive VLB""s 803, 804, 805, 806 comprising a single set of incoming User Data 800 are processed by the Controller 604 (FIG. 6), and essentially form one continuous stack of incoming data.
When data was stored in such a multibank structure according to the prior art, an interleaving process fragments a single Virtual Logical Blocks of data into multiple Physical Memory Blocks. This process can be illustrated in in conjunction with FIG. 8. Consecutive logical blocks 810, 811, 812, 813 within the same Virtual Logical Block 803 are consecutively loaded into the RAM Data Registers 840, . . . , 846 for storage. In the first cycle, Logical Block 21:0810 is loaded into RAM Data Register 1840, Logical Block 21:1811 is loaded into RAM Data Register 2842, Logical Block 21:2812 is loaded into RAM Data Register 3844, and Logical Block 21:3813 is loaded into RAM Data Register 4846. The contents of the four registers 840, . . . , 846 are then simultaneously programmed into the first Pages 858, 861, 864 and 870 within four separate and distinct Physical Data Blocks 850, 852, 854, 856 within the respective Memory Banks 832, 834, 836, 838. Data stored according to this interleaved process therefore fragments a single Virtual Logical Block of Data Across four separate Physical Memory Blocks 850, 852, 854, 856 disposed within four separate Memory Banks 832, 834, 836, 838. When the data were retrieved in a reverse process, it can be reconstructed accurately. However, if a reverse interleaving process is not utilized, reconstruction of the User Data becomes problematic. Although reconstruction can be accomplished through detailed Correlation Fields which correlate LBA""s to PBA""s, the resulting liabilities in memory consumption make this option largely unworkable.
Because the interleaving process is achieved in part to the activity of the Host, a Host designed to work in conjunction with a standard or single-bank Flash Memory Unit can only reconstruct a file of User Data when a single VLB is stored in a single VPB, establishing a one-to-one Correlation between the LBA""s and the PBAs. Older Hosts therefore cannot retrieve data from multiple memory banks that store data in a fragmented or interleaved fashion; the systems are simply not compatible. The problem could theoretically be resolved by designing a multibank flash memory stick with a RAM Data buffer 830, FIG. 8 of sufficient data capacity to store the four incoming Virtual Logical Blocks of data 803, . . . , 806, and perform the interleaving process transparently within the flash memory stick. A Host would simply load data continuously into a RAM Data Buffer of the Flash Memory System. How the Flash Memory System processed the data would be transparent, and therefore irrelevant and to the Host. The obvious drawback is the massive amount of memory which must be set aside for use by the RAM Data buffer. Similarly, the problem could be solved by devoting a massive amount of memory within the Flash Memory System to the RAM the Space Manager. If every single LBA were correlated to every single PBA, fragmentation would not prevent reconstruction of data. Again however, a massive amount of valuable memory would have to be devoted to the random access memory of the Flash Memory System, reducing the actual capacity of the flash memory itself. Although either of these solutions might resolve the problem of designing a Flash Memory System compatible with various Hosts, they do not lend themselves well to Flash Memory applications.
There exists therefore need for a multi-bank flash memory stick which exhibits the speed advantages a multibank Flash Memory Unit, while maintaining downward compatibility with older Hosts designed for traditional single bank Memory sticks. There further exists a need for a Host that can utilize the speed advantages of a multibank flash Memory Unit while storing the data in an arrangement that can later been retrieved by older Hosts. There further exists a need for a user friendly means for configuring a Flash Memory System to store data in a proper arrangement according to the capabilities and format of the Host transmitting the data for storage. There further exists a need for a user friendly means of configuring a Host to send and retrieve data in a format or protocol that is compatible with both traditional single-bank flash memory sticks, and multibank Flash Memory sticks. There further exists a need for achieving compatibility while minimizing the amount of memory expended on the RAM Data buffer. There further exists a need for achieving compatibility with diverse Hosts while minimizing the amount of flash memory expended on the RAM a Space Manager.
The present invention discloses a method and apparatus for storing incoming user data in a multibank Flash Memory System which exhibits the speed advantages a multibank Unit while storing a Virtual Logical Block of data in a non fragmented arrangement, thereby maintaining downward compatibility with older Hosts designed for traditional single Memory Banks sticks. The present invention further discloses a method and apparatus for utilizing the speed advantages of a multibank Flash Memory Unit while storing data in an arrangement accessible to older Hosts. The present invention further discloses a method and apparatus for configuring a multibank Flash Memory System to store data in a proper arrangement according to the capabilities and format of a Host transmitting the data for storage. The present invention further discloses a method and apparatus for configuring a high-performance Host to send and retrieve data in a format or protocol that is compatible with both traditional single-bank flash memory sticks, and multibank Flash Memory sticks. The present invention further discloses a method and apparatus for achieving compatibility with both traditional and high performance Hosts while minimizing the amount of memory expended on the RAM Data buffer. The present invention further discloses a method and apparatus for achieving compatibility with both traditional and high performance Hosts while minimizing the amount of memory expended on the RAM Space Manager.
According to one embodiment of the present invention, a Flash Memory System comprises a plurality of separate and independently addressable Memory Banks. Each Memory Bank comprises a plurality of independently addressable and independently programmable non-volatile Data Storage Areas and a primary RAM Data Register. A first primary RAM Data Register within a first Memory Bank is capable of programming data into Data Storage Areas within the first Memory Bank, and a second primary RAM Data Register within a second Memory Bank is capable of programming data into Data Storage Areas within the second Memory Bank. The Flash Memory System also comprises a Vendor Unique Value, including means for loading the Vendor Unique Value into a Handshake Data Envelope upon start up. When no responsive handshake is received from a Host, the Flash Memory System defaults to a first mode for storing data in a manner compatible with traditional Hosts. When the responsive handshake is received from the Host, the Flash Memory System is configured to a second data storage mode capable all of storing multiple pages of data simultaneously by means of the multiple Memory Banks.
According to one embodiment of the present invention, a Flash Memory System comprises a plurality of separate and independently addressable Memory Banks. Each Memory Bank comprises a plurality of independently addressable and independently programmable non-volatile Data Storage Areas, and a primary and an auxiliary RAM Data Register. A first primary and first auxiliary RAM Data Register within a first Memory Bank are independently capable of programming data into Data Storage Areas within the first Memory Bank. A second primary and the second auxiliary RAM Data Register within a second Memory Bank are independently capable of programming data into Data Storage Areas within the second Memory Bank. When operating in a high-performance storage mode utilizing simultaneous programming of multiple Memory Banks, sequential programming cycles will alternately utilize the primary and auxiliary RAM Data Registers for data storage. The Flash Memory System also comprises a Vendor Unique Value, including means for loading the Vendor Unique Value into a Handshake Data Envelope upon start up. If no responsive handshake is received from a Host, the Flash Memory System defaults to a first mode for storing data in a manner compatible with traditional Hosts. If a responsive handshake is received from the Host, the Flash Memory System is configured to a second mode, capable all of storing multiple pages of data simultaneously by means of the multiple Memory Banks.
According to one embodiment of the present invention, a method of programming incoming data into a multibank Flash Memory System comprising a Vendor Unique Value, a Controller operatively connected to a Memory Unit, the Controller comprising a RAM Data Buffer operatively connected to a Memory Interface Circuit, the Flash Memory Unit comprising a plurality of separate and individually addressable Memory Banks, each Memory Bank comprising a primary RAM Data Register and a plurality of individually addressable and individually programmable Physical Data Blocks, each Physical Data Block comprising a plurality of individually addressable and individually programmable Pages, the method comprising the steps of generating a Handshake Data Envelope, loading the Vendor Unique Value within a Flash Memory System into the Handshake Data Envelope; and sending the Handshake Data Envelope to a Host. If no responsive handshake is received from the Host, the Flash Memory System defaults to a first data storage configuration and programs incoming data into the Flash Memory System according to a first data storage method of programming one page of User Data per programming cycle. If a responsive handshake is received, the Flash Memory System is configured to a second data storage configuration which includes the simultaneous programming of a plurality of pages of data into multiple Memory Banks on each programming cycle. The programming is performed in a non-interleaved fashion so that consecutive Logical Block Addresses within a common Virtual Logical Block Address are stored in consecutive physical block addresses in a common Physical Data Block.
According to one embodiment of the present invention, a method of programming incoming data into a multibank Flash Memory System comprising a Vendor Unique Value, a Controller operatively connected to a Memory Unit, the Controller comprising a RAM Data Buffer operatively connected to a Memory Interface Circuit, the Flash Memory Unit comprising a plurality of separate and individually addressable Memory Banks, each Memory Bank comprising a primary RAM Data Register, an auxiliary RAM Data Register and a plurality of individually addressable and individually programmable Physical Data Blocks, each Physical Data Block comprising a plurality of individually addressable and individually programmable Pages, the method comprising the steps of generating a Handshake Data Envelope, loading the Vendor Unique Value within a Flash Memory System into the Handshake Data Envelope, and sending the Handshake Data Envelope to a Host. If no responsive handshake is received from the Host, the Flash Memory System defaults to a first data storage configuration and programs incoming data into the Flash Memory System according to a first data storage method of programming one page of User Data per programming cycle. If a responsive handshake is received, the Flash Memory System is configured to a second data storage configuration which includes the simultaneous programming of a plurality of pages of data into multiple Memory Banks on each programming cycle. The programming is performed in a non-interleaved fashion so that consecutive Logical Block Addresses within a common Virtual Logical Block Address are stored in consecutive physical block addresses in a common Physical Data Block. Sequential programming cycles will alternately utilize the primary and auxiliary RAM Data Registers for data storage.
These and other advantages will become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawings and figures.